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Stacked Second Level Overvoltage Protectors

Karthik Kadirvel, Robert Taylor, John Carpenter
Texas Instruments

In recent years there has been an increase in the use of multicell Lithium-Ion (Li-Ion) batteries in various applications such as power tools, uninterruptible power supplies (UPS) and hybrid electric vehicles. In these applications, system safety is a primary concern. A second-level over voltage (OV) protector is a device used to improve the system’s overall safety. They are connected across each cell in addition to the primary protector to check if the battery voltage goes above a prescribed threshold. If an over voltage condition occurs, and the primary protector fails to protect the system, the second-level protector usually blows a fuse or turns on a protection FET to prevent a hazardous condition. The key performance metrics for second-level protectors are total solution cost, power consumption and the maximum voltage that the IC can withstand.

Usually, second-level protector ICs are designed for two to six cells stacked in series. As the number of cells increases in a battery pack, a single second-level protector IC cannot be used for all the cells in the battery pack. Multiple ICs are used and each IC’s outputs are combined appropriately using external components. Another solution is to use specialized ICs with communications channels to propagate the fault signal. These solutions could lead to increased cost and power consumption. This article presents a solution to the problem of designing a second-level protector for a multi-cell battery using multiple ICs without an increase in external component count or increased power consumption.

Background and Theory of Operation Fig1
For the example in this article, based on the battery chemistry and application, we used the BQ2941x [1] family of second-level OV protector ICs, where x denotes the trip voltage. These devices are designed for four series cell and have a very low quiescent current consumption of 2 uA. The techniques used couple the IC’s output to a common fault line using opto couplers [2]. This approach adds complexity and cost. In some ICs special pins are used to transmit the top IC’s fault to the IC below it, which is then propagated to the bottom most IC.

The simplified solution presented here consists of using the fault output signal of each IC in the stack as the top cell input to the IC below it. This technique is demonstrated using the BQ2941x family of second-level OV protectors. In these ICs, VC1 to VC4 represent the cell inputs. The output fault signal is available at the OUT pin. The time delay between the fault’s occurrence and the actual output fault signal going high is determined by an external capacitor connected to the CD pin.

Figure 1 shows a schematic of two second-level OV protector ICs in the stacked configuration. The top IC’s OUT pin is connected to the VC1 bottom IC’s input. The top IC’s CD pin is left floating or connected to a very small (<1nF) capacitor. In these ICs, the OUT signal is held low as long as the voltage for each cell is below the trip threshold. Under normal operation (no fault), the voltage level at the top IC’s OUT signal equals the voltage at node VC3. Thus, the bottom IC does not have a fault condition. During a fault condition the OUT pin is pulled high. Logic high for this IC has a nominal voltage of 7V[2]. This voltage is much higher than the IC’s OV threshold. Hence, when a fault signal is created on the top IC, the OUT signal can be used to create a fault on the IC below it and cause its OUT signal to go high. This technique can be expanded to multiple ICs to propagate the fault from any IC in the stack to the bottom most IC.

Fig2 The system’s time delay is determined by the capacitor connected to the bottom IC. The stacked system shown in Figure 1 can protect a seven-series (7S) cell battery pack. Each additional second-level OV protector IC can protect three more series (3S) cells. To test this theory, the system is verified with simulations and experimental results.

Simulation and Characterization Results
An IC’s transistor level SPICE model is used to simulate the circuit in Figure 1. You can see the simulation results in Figure 2. For the simulation, each cell is held to a voltage below the trip threshold. The second cell in the top IC (VC6 – VC5) was changed to 5 V to simulate a fault condition. The OUT signal of the bottom IC goes logic high, which creates an over voltage condition. The top IC output goes high after a very short delay. Then the bottom IC OUT goes high. The negligible delay of the top IC is determined by the parasitic capacitance and the small capacitor connected to the CD pin. The delay time for the bottom IC OUT to go high of ~68 ms is determined by the capacitor (10 nF) connected at the bottom IC’s CD pin.

Fig3 Figure 3 shows a plot of the experimental results. The differential voltage between nodes VC5 and VC6 is shown. The cell voltage goes from a nominal voltage of 2.5 V to 5 V, which creates an OV condition. The top IC OUT signal and the bottom IC OUT signal are also shown on the same plot. The top IC OUT signal goes high immediately due to the small capacitance at its CD pin. The bottom IC OUT signal goes high after a time delay. The overall delay time is approximately 65 ms. This is determined by the 10nF capacitor connected to the bottom IC CD pin. The delay time matches well with the simulation results presented in Figure 2.

It is important for the stacked configuration to consume the same amount of quiescent current as a single IC. The current consumption from the battery pack for the single IC and two IC configurations were verified to be approximately 2 uA and match the published specifications in the data sheet.

Conclusions
A brief overview of existing second-level over voltage protectors was presented. A novel solution stacks multiple ICs to increase the number of cells that can be monitored. This is done without an increase in external component count or current consumption. The technique was simulated and experimentally verified.

References
[1] “Voltage Protection for 2-, 3-, or 4-Cell Li-Ion Batteries (2nd-Level Protection),” Data Sheet, Texas Instruments, 2005: www.ti.com/bq29410datasheet-ca.
[2] Williams, Doug, “Stacking Multiple bq2941x Li-Ion Secondary Voltage Protectors,” Application Report, Texas Instruments, SLUA434, August 2007: www.ti.com/bq2941xappnote-ca.

About the Authors
John Carpenter, Jr., is Senior Design Engineer and Supervisor responsible for system level integration and IC design with multifaceted circuits for mixed signal applications in BICMOS processes. He received his MSEE and BSEE from the University of South Florida, Gainesville. John holds 11 patents and is a Senior Member of IEEE, Senior Member Technical Staff for Texas Instruments, and a Qualified Naval Engineering Duty Officer for US Navy Reserves.

Karthik Kadirvel is a circuit designer responsible for design and characterization of analog and mixed signal ICs. Karthik received his PhD from the University of Florida, Gainesville and is a member of IEEE.

Robert Taylor is an Applications Engineer and a Member Group Technical Staff at Texas Instruments where he provides high-volume customers with power reference designs. Robert received his MSEE and BSEE from the University of Florida, Gainesville.